1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device which in particular has multiple transistors having different withstand voltage characteristics formed on the same semiconductor substrate.
2. Background Information
In recent years, technology for forming multiple transistors with different withstand voltage characteristics has been developed (e.g. Japanese Laid-Open Patent Application No. 2000-349164 (hereinafter to be referred to as Patent Reference 1)).
Generally, a semiconductor device applying such technology for forming multiple transistors with different withstand voltage characteristics has a structure in which a MOS (Metal Oxide Semiconductor) transistor having a gate oxide with a first thickness (to be referred to as a first gate oxide) and a MOS transistor having a gate oxide with a second thickness (to be referred to as a second gate oxide) which is thicker than the first gate oxide are formed in a single semiconductor substrate. In the following description, the MOS transistor having the first gate oxide will be referred to as a high voltage MOS transistor, and the MOS transistor having the second gate oxide will be referred to as a low voltage MOS transistor. Moreover, a region in which the high voltage MOS transistor is to be formed will be referred to as a high voltage region, and a region in which the low voltage MOS transistor is to be formed will be referred to as a low voltage region.
Now, one example of a method of manufacturing such semiconductor device as mentioned above will be shown. In this manufacturing method, first, a field oxide is formed in the semiconductor substrate by a LOCOS (local oxidation of silicon) method for instance. Next, by conducting a thermal oxidation treatment on the surface of the semiconductor substrate, the first gate oxide is formed on the entire film of the semiconductor substrate. Next, the high voltage region is covered by a photoresist, and under this state, the first gate oxide is etched to expose the semiconductor substrate in the low voltage region. After that, the photoresist is removed, and then the entire surface of the semiconductor substrate is oxidized to form the second gate oxide in the low voltage region.
However, according to the above-described method, the comparatively thick first gate oxide gests over-etched, and thereby, the upper surface of the element separating insulation film (i.e. the LOCOS film) is also etched. Therefore, it has been a problem that the semiconductor substrate in the vicinity of a bird's-beak part of the element isolating film gets exposed.
A method for coping with such problem is disclosed in Patent Reference 1, for instance. In the following, this technology will be referred to as prior art technology 1. According to the prior art technology 1, first, a field oxide is formed in a semiconductor substrate using the LOCOS method, after which an oxide film (i.e. a buffer film) and a nitride film (i.e. a protective film) are formed sequentially. Next, by patterning this laminated structure, a high voltage region is exposed. Next, by conducting thermal oxidation on the exposed surface of the semiconductor substrate, a first gate oxide is formed. Next, the oxide film and the nitride film covering a low voltage region are removed, and then by conducting thermal oxidation on the surface of the semiconductor substrate exposed by removing these films, a second gate oxide is formed.
In this way, since the low voltage region is covered by the protective film at the time of forming the first gate oxide, it is not necessary to etch the first gate oxide at the time of forming the second gate oxide. Therefore, according to the prior art technology 1, it is possible to prevent the semiconductor substrate in the vicinity of a bird's-beak part of the field oxide from becoming exposed due to over etching at the time of removing the first gate oxide.
In addition, there are other methods of eliminating the process of etching the first gate oxide, such as the one introduced in Japanese Patent No. 3107582 (hereinafter to be referred to as Patent Reference 2). In the following, technology introduced in the Patent Reference 2 will be referred to as prior art technology 2. According to the prior art technology 2, a nitride film (i.e. a protective film) used in forming a field oxide by a LOCOS method is applied in forming a first gate oxide only in a region of a high voltage region where a gate electrode is to be formed. In this way, the process of etching the first gate oxide can be eliminated.
However, according to the prior art technology 1, the first gate oxide which is comparatively thick is formed on the entire surface of an element formation region (also called an active region) in the high voltage region, and therefore, at the time of forming doped regions, which function as a source and a drain, the first gate oxide of these regions needs to be etched. This can cause a problem that the field oxide on the side of the high voltage region gets etched and becomes thin. Particularly, in a semiconductor device having a structure in which a high voltage region is divided into three active regions (i.e. a region where a channel is to be formed, and a pair of regions where a source and a drain are formed) by field oxides, when the field oxides defining each active region becomes thin, it may lead to a problem that a withstand voltage characteristic etc. may be deteriorated.
According to the prior art technology 2, the protective film used in the LOCOS method is used as a protective film in forming the first gate oxide. Therefore, at the time of forming the first gate oxide, the field oxide in the low voltage region becomes thick as with the field oxide in the high voltage region. When the field oxide in the low voltage region becomes thick in this way, a response characteristic of the low voltage MOS transistor, which requires high-speed operation as compared with the high voltage MOS transistor, may be deteriorated, and this may cause a problem in which a required operation characteristic may not be obtained.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved method of manufacturing a semiconductor device. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.